SDRAM Tutorial

Technical Data

In this section you'll get some technical data and explanation about how SDRAM actually works.

The SDRAM is, as noted before, a variation of DRAM. As such, the SDRAM also stores bits of data using a transistor and a capacitor instead of the six of them used in Static RAM. Given an address to read from or store to, the necessary transistors "open" and the capacitor is charged to the input value, or the stored voltage is outputted. In order to mitigate capacitor leakage all rows are refreshed occasionally  in order to refresh the voltage even if no outside request is made. Other than its synchronous nature, the SDRAM also has the capability of pipelining commands rather then only handling one write request at a time, this is a result of the greater chip complexity of the sdram.

The SDRAM itself does not handle higher level  handling of outside requests. Managing the SDRAM and assuring it handles requests correctly is done by a controller that translates the requests of the host into control signals to the SDRAM while keeping trackof the SDRAM's state. The controller also translates the SDRAM's output signals for the host. Because of this, no analysis of the SDRAM can be complete without also analyzing the controller, an analysis done in the next part of the tutorial.

The SDRAM itself has the following control signals:

CKE - Clock Enable. This signal masks the SDRAM clock signal, while CKE is '0' no rising clock edge can be detected and the SDRAM stops until CKE is '1' again.

CS  - Chip Select. When this signal is '1' the SDRAM ignores all signals received from the controller except for CKE.

DQM - Data Mask(the q is due to a convention that that the data lines are called DQ lines). When '1', these signals suppress data read/write. write commands are not executed while the mask is '1' and if asserted two cycles before a read cycle, no data is read (output does not change to the data in the address).

RAS and CAS row/collum address strobe, not in fact a strobe. Instead along with WE those 3 signals determine what command the SDRAM receives from the controller.

WE - Write enable. The 3rd signal determining what command is received. generally only high during write operations. 

In addition to the control signals the SDRAM also has input busses to recieve row, colummn and bank adress from the controller as well as data to to written (the same bus is also used to send read data to the controller). Collum addresses are only 11 bits and so can be represented using A0-A9 and A11, and some of the commands do not require an address.

 The following commands can be sent using the control signals :

ACTIVATE - This command gives the SDRAM a bank address (2 bits deciding which of the up to 4 banks the sdram can possess is addressed now) and a row address (the row address also requires the A10 bit so it has no special use for the command). The contents of row of the bank is read into the array of column content sense amplifiers of the bank, the data is now available for access. As a side effect the activation also refreshes the charge on that row's capacitors helping to prevent loss of data. The activation is not immediate, and so during the row to column time Read and Write operations cannot be performed on the bank, although the other banks can still be accessed, enforcing this time limitation on incoming requests is handled through the SDRAM controller.

READ / WRITE - Once a bank has been activated, requests for the current row can be handled. A read request would cause the SDRAM to send the Data in the row to the DQ lines  after the cas latency time(2 or 3 clock cycles). A write request  causes the data in the DQ lines to be written to the bank's row.

Precharging - Once a row has been activated , it must be 'closed' before a new row can be activated, this is because the sense amplifiers in the bank must be returned to idle state, so the next row's content can be read. There are two ways to command the SDRAM to precharge. The first is through the precharge command that according to the value of A10 Either charges  the chosen bank, or all banks. The second is by appending a read/write request with a precharge request, done by sending a read/write command with A10 on High.

Auto refresh - The auto refresh command refreshes a row in each bank, the banks must be precharged for the refreshing to be possible , the SDRAM has an internal counter that causes it to change the selected row every refresh interval(t,ref) and so the controller can prevent data loss due to capacitor leakage by sending an Auto refresh command every refresh interval so the rows are refreshed as soon as possible.

Mode loading - The SDRAM has 10 bits M0-M9 that define the mode it is working in.
When the Mode loading command is given each of the bits M0-M9 receives the value of the address bit of the same number (A0->M0.)

The bits control:

M9- Decides if the SDRAM would be in burst or no burst write(read is always in burst mode)
M8 and M7 - Reserved and must be defined as '0' when the Mode is loaded
M6 ,M5 and M4 - Define the CAS latency, typically It would be either 2(0,1,0) or 3(0,1,1)
M3 - Defines if the SDRAM uses sequential burst or interleaved burst
M2,M1 and M0 - Define the size of read bursts and write bursts. If M9 is '1', the size can be 1,2,4 or 8 words.

The amount of cycles each command takes to  be resolved is dependent on the SDRAM's design parameters and the clock frequency used, so in order to avoid commands being given to the SDRAM that it can not yet resolve, the Controller must be programmed with the timing values of the SDRAM it is meant to control. As you can see from the technical analysis of the SDRAM, it has no direct contact with its host. Instead, all requests are  handled by the controler which sends the appropriate control signals to the SDRAM.

In order to fully understand how the sdram works, it is thus necessary to explain how the controller works. To that purpose the tutorial includes both a written explanation and an interactive simulation to help understand the controller.

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