SDRAM = Synchronous Dynamic Random Access Memory
To understand SDRAM, first you'll have to understand what RAM (Random Access Memory) is. Then we'll explain the differences between DRAM (Dynamic RAM) and SRAM (Static RAM). Finally we'll explain the differences between SDRAM (Synchronous DRAM) and ADRAM (Asynchronous DRAM) .
RAM (Random Access Memory) is a form of computer data storage. Today, it takes the form of integrated circuits that allow stored data to be accessed in any order. "Random" refers to the idea that any piece of data can bereturned in a constant time regardless of its physical location and whether it is related to the previous piece of data.
SRAM (Static RAM) works on the principle of a switch that is turned on or off and requires 2 to 4 transistors for each bit (a bit has two states; on or off and is the smallest unit of memory storage and is made of one memory cell).
DRAM (Dynamic RAM), on the other hand, is based on a capacitor's ability to hold a charge and requires only one transistor per bit. Because DRAM cells are smaller than SRAM, manufactures can put more memory into the same size thus reducing the cost per bit. Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory.
Because the bucket has holes in it, someone needs to keep adding water to maintain the water level. We call this refreshing the bucket and we send George down to put more water in as needed. When George refreshes a bucket, he needs to know if the bucket has water in it or not, so he looks at the bucket and adds more water if it has some water in it. If George doesn't refresh the bucket often enough, he will not know if it is supposed to contain water and we lose information. We must keep sending George down to refresh at a rate that is faster than the holes can drain the water.
This is a basic Dram memory unit
DRAM uses refresh circuitry for the purpose of maintaining the charge and thus information stored, while SRAM does not need refresh because it has better and more expensive buckets without the holes in them. Should the refresh cycle be interrupted for any length of time, we lose the information in memory. Paying George to keep the buckets full of water is a constant cost, but by hiring George we save the higher cost of good buckets.
Sometimes we want to read the data or look and see if the bucket is full of water (a '1') or empty (a '0'). Because we are working with leaky DRAM buckets, George has to make a determination as to what the level of water is in the bucket to determine if it is a 1 or 0. He has to do this, because some of the water will have leaked out since the last refresh cycle. If the bucket is 1/2 or less, then it is a '0', but if the bucket is more than 1/2 full then it is a '1'. George must now stop and measure the level of water with a ruler which takes a little time. This decreases the speed at which memory can run. DRAM is more than a digital device, with only levels of 0 and 1; internally it is an analog device with a level detector. Level detectors requires a small amount of time to determine if we have a '0' or a '1' in a cell. This extra time is one reason SRAM runs faster than DRAM.
SDRAM (Synchronous DRAM) is a DRAM that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs. SDRAM has a synchronous interface, meaning that it waits for a clock signal before responding to control inputs and is therefore synchronized with the computer's system bus. The clock is used to drive an internal finite state machine that pipelines incoming instructions. This allows the chip to have a more complex pattern of operation than an asynchronous DRAM, enabling higher speeds.
Pipelining means that the chip can accept a new instruction before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another instruction without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears after a fixed number of clock pulses after the read instruction, cycles during which additional instructions can be sent. (This delay is called the latency and is an important parameter to consider when purchasing SDRAM for a computer).